The present invention relates to phase-locked loops (PLLs) and, in particular, to a dual-loop integrated PLL having an on-chip loop filter and an off-chip loop filter.
PLLs are used in integrated circuits, such as application specific integrated circuits (ASICs), for clock synchronization, recovery of serial data streams and frequency synthesis. A typical PLL includes a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO) and a frequency divider. The VCO generates a clock signal with a phase and frequency that is a function of the voltage applied to the oscillator. The phase/frequency detector detects a phase and/or frequency difference between the VCO output and the input signal. The phase/frequency detector generates a control signal as a function of the difference and applies the control signal to the charge pump which increases or decreases the voltage across the loop filter. This voltage is applied to the VCO for controlling the oscillation frequency and phase of the clock signal.
In a PLL fabricated on an integrated circuit, it is often desirable to have the loop filter external to the integrated circuit. With an off-chip loop filter, filter component values can be easily changed to accommodate a specific application, and the filter cut-off frequency can be tightly controlled since the discrete resistor and capacitor which form the loop filter are economically available with values having 1-5 percent tolerances. Lower cut-off frequencies are also achievable with an off-chip loop filter, as opposed to an on-chip loop filter. Low-leakage, very low-cost ceramic capacitors are available with capacitances up to 100,000 pF, whereas the maximum economical on-chip capacitor is on the order of 10's of pF. For applications requiring a lower filter cut-off frequency, such as in high resolution frequency synthesis, an on-chip loop filter is difficult.
However, a significant problem results when the loop filter is brought off-chip. The loop filter output is coupled to an external pin on the integrated circuit which, in turn, is coupled to the frequency control input of the voltage-controlled oscillator. For a wide-band, low Q, ring-oscillator type VCO, the frequency control input of the VCO is always a high-gain input. For a 100 MHz PLL of this type, the VCO gain (K.sub.VCO) is usually designed to be at least 100 MHz/V, and sometimes as high as 1,000 MHz/V. With an off-chip loop filter, the high-gain frequency control input is exposed to switching noise from the circuit board on which the integrated circuit is mounted and from switching noise adjacent to the external pin. This noise shows up in the PLL output as jitter in the time domain and as spurs in the frequency domain. A PLL having an off-chip loop filter and which is less susceptible to switching noise is desired.